Multiple mark detectors for end marked switching networks

ABSTRACT

A SWITCHING SYSTEM UTILIZING AN END MARKED NETWORK HAS CIRCUITRY FOR DETECTING THE PRESENCE OF DOUBLE MARKS ON EITHER SIDE OF NETWORK. THE NETWEOK FUNCTIONS IN THE CONVENTIONAL MANNER TO COMPLETE A CONNECTION BETWEEN A LINE SIDE AND TRUNK SIDE CIRCUIT IN RESPONSE TO THE APPLICATION OF A SINGLE MARK OF EACH SIDE. IN RESPONSE TO THE SIMULTANEOUS APPLICATION OF TWO OR MORE MARKS TO EITHER SIDE, THE DETECTION CIRCUITRY RECOGNIZES THIS AS A TROUBLE CONDITION, GENERATES AN ALARM SIGNAL, AND PREVENTS THE NETWORK FROM ATTEMPTING TO RESPONDS TO THE SIMULTANEOUSLY APPLIED MARKS.

14, 1974 E. THELEMAQUE 28,007

MULTIPLE MARK DETECTORS FOR END MARKED SWITCHING NETWORKS Original FiledMay 21, 1971 8 Sheets-Sheet 1 2. VIE F525 M 2 E E .E 22: a I. .l m E .I2 II I. 26% w I. 122: F u m M 0: 3 S I: 525 w E E. 22: f I- m C 02 8 s H56% 7 m OI V m 9 OS 85:5 x22:

/Nl//V7OR L. E THELEMAQUE QW J WM ATTORNEY May 14, 1974 L. E. THELEMAQUEMULTIPLE MARK DETECTORS FOR END MARKED SWITCHING NETWORKS Original FiledMay 21, 1971 8 Sheets-Sheet 2 voo gvlo gm m QHO H00 HIO H70 H6. 24

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FIG. 48 FIG. 4D

May 14, 1974 L. E. THELEMAQUE Re. 28,007

MULTIPLE MARK DETECTORS FOR END MARKED SWITCHING NETWORKS Original FiledMay 21, 1971 8 Sheets-Sheet 5 7 w m m 7 L L U fi m m 7 7 J Y llll II C CA Ii 7 O H O H H W 7 H H H v H v w v V A A 1 A I U I A I 2 III I l 0 Ill H a AH EH w L 0 mm 4 Ew 4 a... M A WU A o 5 3 5 r H H Q L 7 ll [I w wWN m K H QM: H v -H H W QEQO V -v 7 I F 0 P B B r \A1 2 COMMON CONTROL y1974 1 E. THELEMAQUE Re. 28,007

MULTIPLE MARK DETECTORS FOR END MARKED SWITCHING NETWORKS Original FiledMay 21, 1971 8 Sheets-Sheet 4 FIG. 3B

" TRUNK SWITCH 0 El L 55 y L70 (mp TRUNK 4 SWITCH 7 D2 DI" L77 H7 May14, 1974 E. THELEMAQUE 23,007

MULTIPLE MARK DETECTORS FDR END MARKED SWITCHING NET'ORKS Original FiledMay 21, 1971 8 Sheets-Sheet BINARY COMPLEMENT ENCODER us VERTICALTRANSLATORV y 14, 1974 L. E. THELEMAQUE Re. 28,007

MULTIPLE MARK DETECTORS FOR END MARKED SWITCHING NETWORKS 8 Sheets-Sheet6 Original Filed May 21, 1971 25 n & 8:

14, 1974 L. E. THELEMAQUE Re. 28,007

MULTIPLE MARK DETECTORS FOR END MARKED SWITCHING NETWORKS May 14, 974 L.E. THELEMAQUE 23.007

MULTIPLE ARK DETECTORS FOR END MARKED SWITCHING NET'ORKS B Sheets-Sheet8 Original Filed May 21, 1971 Ymmq United States Patent Oflice Re.28,007 Reissued May 14, 1974 Matter enclosed in heavy brackets [IIappears in the original patent but forms no part of this reissuespecification; matter printed in italics indicates the additions made byreissue.

ABSTRACT OF THE DISCLOSURE A switching system utilizing an end markednetwork has circuitry for detecting the presence of double marks oneither side of the network. The network functions in the conventionalmanner to complete a connection between a line side and a trunk sidecircuit in response to the application of a single mark on each side. Inresponse to the simultaneous application of two or more marks to eitherside, the detection circuitry recognizes this as a trouble condition,generates an alarm signal, and prevents the network from attempting torespond to the simultaneously applied marks.

BACKGROUND OF THE INVENTION This invention relates to a switchingsystem, and in particular to a switching system having an end markednetwork. The invention further relates to a switching system havingfacilities for detecting the application of more than one marksimultaneously to either side of an end marked network.

Switching systems equipped with end marked networks are known. In suchsystems, connections are established between the line side and trunkside circuits by applying marking potentials to the network. The networkresponds to the marking potentials and establishes a connection betweenthe two circuits whose terminals are marked.

End marked networks are said to be self-controlled in that they operateon their own to select and establish connections between trafiiccircuits associated with marked terminals. The use of such networkslessens the complexity of the system control circuitry. The reason forthis is that in order to establish a connection between a specified lineside and a specified trunk side circuit, the only requirement of thesystem control is that it apply a marking potential to the networkappearances of the two circuits. The network responds to the markingpotentials, determines whether an idle path is available, and if it is,establishes the path it selects. This mode of operation frees the systemcontroller from the task of determining which of a plurality of idlepaths is to be used on a given connection.

Although the use of an end marked network simplifies the design of thesystem controller, systems of this type are vulnerable to troubleconditions and malfunctions which cause two or more marks simultaneouslyto be applied to either side of the network. Specifically, if due to atrouble condition, two terminals are marked simultaneously on its lineside while a single terminal is marked on its trunk side, the network isobviously unable to determine which of the two marked line side circuitsis to be connected with the marked trunk side circuit. Under suchconditions, the network either establishes unwanted paths in addition tothe correct path, destroys existing paths, or alternatively establishesno path at all and causes the system controller to energize a time outalarm after the call connection is not completed within a predeterminedtime. None of these alternatives is satisfactory. The establishment oferroneous paths or the destruction of existing paths is obviously not anacceptable operational characteristic. The actuation of the time outalarm does little, if anything, to identify the nature of the troublesince this alarm is indicative of many different possible troubleconditions.

BRIEF SUMMARY OF THE INVENTION 1. Objects It is therefore an object ofthis invention to provide facilities for detecting the application oftwo or more marks simultaneously to either side of an end markednetwork.

It is a further object of the invention to prevent the network fromresponding to the simultaneous application of double marking potentials.

It is a further object to provide alarm facilities for indicating adouble marking condition of the network.

2. Summary Description A switching system is provided in accordance withthe present invention having facilities for detecting the application ofdouble marking potentials simultaneously to either side of an end markednetwork, for preventing the network from responding to these markingpotentials, and for actuating an alarm to indicate the specific natureof the trouble condition. The system includes two translators, one foreach side of the network. Each translator has an input individual toeach marking conductor connected to an appearance on its side of thenetwork. The translator responds to the reception of a marking potentialon any of its inputs and, in response thereto, generates outputinformation identifying the network switch to which the energizedmarking conductor is connected, as well as the particular switchvertical or horizontal serving the energized conductor. The output ofthe translator is connected to a pair of encoders. The first of these istermed a binary encoder and it generates a binary representation of thetranslator output information, namely the switch number, and switchvertical (or horizontal) for the marked terminal. The second of thesetranslators is termed a binary complement encoder and it generates thebinary complement of the output of the first encoder.

The outputs of the two encoders are applied to a comparison circuitwhich determines whether the outputs are complementary in each of theirbinary orders. The output of the comparison circuitry is connected tothe network controller in such a manner that the network is permitted torespond to marking potentials and establish a path only if the outputsof the two decoders are complementary. This complementary condition willprevail whenever a single marking potential is applied to each side ofthe network. However, when two or more marks are simultaneously appliedto a side, its two encoders generate output information that is notcomplementary. The comparison circuitry detects this noncomplementaryrelationship. inhibits the network path establishing circuitry andgenerates analarm condition indicative of the double marked systemcondition.

The encoders are of such a design that in response to input signalsindicating multiple marks, the output of each encoder represents anORing of the outputs it would generate if each mark had been receivedindependently of the other. Under such conditions, the output of thecomplement encoder for each of its bit orders is no longer thecomplement of the output of the ainary encoder. In other works, incertain of the bit orlers, the outputs of the two encoders are the samerather han complementary. This turns on the AND gates for he orders forwhich the encoder outputs are not complenentary. The turn on of one ormore AND gates actuates he alarm, inhibits the operation of the networkcontroller md prevents the establishment of any network path.

In addition to its double mark detection capability, he circuitry of myinvention also detects malfunctions n the path control relays. Theserelays are connected the output of the binary encoder and they areselecively operated by it to close the necessary network :rosspoints. Amake contact of each of these relays is :xtended through logic circuitryto the aforementioned \ND gates. If a relay remains operated and failsto *elease after its path establishement operations for a con- ICCIIOIIhad been completed, the contacts of this relay will :upply an unwantedbinary l to its AND gate when a 'equest for a new network path issubsequently received. Provided that the output of the binary encoder atthis time ioes not specify the operation of the defective relay, thenforrnation then applied to the AND gate associated with he defectiverelay will destroy the complementary rela- .ionship between the encoderoutputs. This causes the AND gate to turn on and indicate a troublecondition in :he same manner as already mentioned.

FEATURES A feature of this invention is the provision of circuitry fordetecting the application of double marking potentials to end markednetworks.

A further feature is the provision of circuitry responsive to thedetection of the double marking potentials for preventing the networkfrom responding to the potentials, and for generating an alarmindicating the specific nature of the system trouble condition.

These and other objects and features of the invention will becomeapparent from a reading of the following description of the inventiontaken in conjunction with the drawing in which:

DRAWING FIG. 1 diagramatically disclose a switching system having a twostage end marked network; and

FIGS. 2A and 2B disclose a ferreed matrix switch of the eight by eighttype.

FIGS. 3A and 38, when arranged as shown on FIG. 5, disclose the controlcircuitry for ferreed network windmgs.

FIGS. 4A, 4B, 4C and 4D, when arranged as shown on FIG. 6, illustratethe circuitry provided in accordance with the present invention fordetecting the simultaneous application of more than one mark to eitherside of an end marked network.

DESCRIPTION The present invention is shown as embodied in a twostagenetwork of the type shown generally in FIG. 1. This network has eightline side switches designated LSO through LS7 and eight trunk sideswitches designated TSO through TS7. Each switch is of the eight byeight type in that it has eight horizontals and eight verticals. Eachline switch serves eight line circuits and each trunk switch serveseight trunk circuits. The line circuits are connected to the switchverticals. The trunk circuits connected to the switch horizontals. Theline circuits and the trunk circuits are designated in octal form. Thusthe line circuits for line switch LSO are designated LC00 through LC07and the line circuits for line switch LS7 are designated LC70 throughLC77. In a similar manner, the trunk circuits are designated octallyTC00 through TC77.

Each line side switch has eight links connected to its horizontals witheach link extending from the line switch to a vertical of a differentone of the trunk switches. Thus, i L00 co nects hor zontal H0 at lineswitch 0 'with vertical VO of trunk switch 0, link L07 connects lineswitch 0 with trunk switch 7. Each line circuit and each trunk circuitis connected to the network by four conductors designated T, R, S and M.The T, R and S conductors are the conventional tip and ring sleeveconductors and they are extended through the network when it establishesa path between a line side and a trunk side circuit. The M conductorsare unique to end marked networks and each such conductor extends onlyto the network appearance of tis tratfic circuit. In a manner well knownin the art, the network responds to marks on the M conductors tocomplete a network path between the circuits associated with markedconductors.

FIGS. 2A and 2B disclose further details of the individual switcheswhich comprise the network shown of FIG. 1. FIGS. 2A and 28 togethershow a coordinate array of ferreed switches arranged to form a matrixswitch. FIG. 2A illustrates the manner in which the control windings ofthe individual ferreed switches are interconnected. FIG. 2B illustratesthe manner in which the crosspoint contacts are arranged to permit anyswitch vertical to be connected to any horizontal.

Ferreed switches per se are well known in the art. They are described inthe T. N. Lowery US. Pat. No. 3,037,085 of May 29, 1962 and in the BellSystem Technical Journals for January 1960 vol. 39 No. 1 on pages 1through 30 in an article entitled, The Ferreed A New Switching Device"by Messrs. A. Feiner, C. A. Lovell, T. N. Lowery, P. G. Ridinger.Further information concerning ferreed switches is shown in the BellSystem Technical Journal, January 1964, in an article by A. Feinerentitled The Ferreed" on pages 1 through 14.

On FIG. 2A each ferreed switch has two control windings, such as thewindings V00 and H00 for the switch at the upper left-hand crosspoint.Winding VOO is termed the column control winding; HOO is termed thehorizontal control winding. On FIG. 2B the contacts are arranged in amatrix array corresponding to that of the control windings. Thus,control windings VOO and H00 together control the operation and releaseof the contacts common to the HO, VO crosspoint on FIG. 2B.

The horizontal control windings of a row are connected in series witheach other and in turn to a row conductor, such as HO for row 0; thevertical windings of a column are connected in series to a columnconductor, such as V0. The top of each column conductor and the left endof each row conductor are connected to a bus designated CC. Thisconfiguration is known in the art as a Haywood bus and is described inthe US. patent to W. S. Haywood, Jr. US. Pat. No. 3,110,772 of Nov. 12,1963. The energization of either one, but not both, of the controlwindings of a ferreed releases its switch contacts. The energization ofboth windings simultaneously closes its contacts. A connection can beefiected between the conductor of a selected row and column by applyinga marking potential to their control conductors. For example, on FIG. 2Athe energization of row control conductor HO and the vertical conductorV0 closes the switch contacts of the upper left crosspoint on FIG. 28.It also releases the switch contacts on other crosspoints for row 0 andvertical 0 Thus, after a connection between the row 0 and vertical 0conductors on FIG. 2A is effected all connections to these conductorsfrom other crosspoints that may have been closed are released.

FIGS. 3A and 38, when arranged with respect to each other as shown onFIG. 5, disclose the circuitry required for controlling the switchcrosspoints of a two stage network. Line switches 0 through 7 are shownon FIG. 3A; trunk switches 0 through 7 are shown on FIG. 3B. Thesefigures disclose only the circuitry that closes or releases the switchcrosspoints, and therefore only the control windings of the sw t hes areshown.

Pulser 301 on the bottom of FIG. 38 generates the potentials required toenergize the control windings. The circuit of FIG. 3A includes contactsof relays Al, A2, A4 and B1, B2 and B4. Similarly, the circuit of FIG.3B includes contacts of relays D1, D2, D4, E1, E2 and E4. These relaysare operated in the manner subsequently described to interconnect theoutput conductors 303 and 304 of the pulser 301 with the controlwindings of the crosspoints that are to be closed.

For example, let it be assumed that it is desired to establish aconnection between line circuit 0 and trunk circuit 0. Line circuit 0 isserved by vertical V0 of line switch 0; trunk circuit 0 is served byhorizontal H0 of trunk switch 0. The only link that interconnects lineswitch 0 with trunk switch 0 is link L00. This link includes relaycontacts CO; on its left end it is connected to horizontal H0 of theline switch 0 and on its right end it is connected to vertical V0 oftrunk switch 0. Thus, the interconnection of line circuit 0 with trunkcircuit 0 requires the use of link L00, the closure of make contacts C0,and the closure of crosspoints 00 on both line switch 0 and trunk switch0. As already mentioned the closure of a selected set of crosspointcontacts requires the energization of both of the ferreed controlwindings common to the crosspoints. Thus, the connection now beingdescribed requires the energization of control windings V00 and H00 online switch 0 and trunk switch 0.

From an inspection of the circuitry associated with the contacts of theA- and B- relays, it may be seen that output conductor 303 of the pulserwill be connected to control conductor V0 of line switch 0 when all ofthe A- and B- relays are released. At that time a path may be traced viaconductor 303 to terminal 307, through break contacts B4 and B2 and B1to terminal 308, and from there through break contacts of relays A4, A2and A1 to the conductor V0 of line switch 0.

From an inspection of the circuitry associated with the E- and D- relayson FIG. 3B it may be seen that the output conductor 304 of the pulserwill be connected to the control conductor H0 of trunk switch 0 when allof the D- and E- relays are released. At that time, conductor 304 isextended to terminal 309 and from there via break contacts E4, E2 and E1to terminal 313, through break contacts of relays D4, D2 and D1 to thecontrol conductor H0 of the switch. At this time, and with relay C0operated, the control windings V00 and H00 of both switches areeffectively in series with each other and with the output of the pulser.When the pulser generates an output pulse, current flows through bothcontrol windings for crosspoints 00 on each of the two switches. Thiscurrent, as already described, closes the make contacts of thecrosspoints and interconnects their T, R and S conductors. This samecurrent flows through the other control windings for vertical 0 and thehorizontal 0 of the same two switches. This current flowing through onlysingle windings of each of these other crosspoints releases theircontacts in the event that they were in an operated state. The time atwhich the pulser 301 sends out the current required to close a set ofcrosspoints is under the control of common control 302. This isdescribed in detail subsequently.

FIGS. 4A through 4D, when arranged with respect to each other as shownon FIG. 6, disclose the circuitry provided in accordance with myinvention for detecting the application of more than one mark at a timeto either side of the network. The equipment within rectangle 401 isshown in detail and performs this double marked detection function forthe line side of the network. The corresponding equipment for the trunkside is shown only diagrammatically by rectangle 402 since it containscircuitry identical to that of rectangle 401.

Line circuits L000 through 77 are shown on the left side of FIG. 4A. TheT, R and S conductors of each line circuit are not connected to thecircuitry of FIGS. 4, but instead, extends to the crosspoint contacts ofthe variout switches as shown on FIG. 1. The M conductor of each linecircuit extends to an input of a vertical translator 403 (FIG. 4A) andto an input of a switch translator 404 (FIG. 4B). The function of thevertical translator is to provide an output signal indicating the switchvertical serving a line circuit having an energized M lead. Similarly,the function of the switch translator is to provide an output signalidentifying the switch that serves the marked line circuit. The outputsof the two translators together uniquely identify the line circuit.

Let it once again be assumed that line circuit 00 is to be connected totrunk circuit 00. The M lead of this line circuit is designated M00 andit extends to gate V0 in the vertical translator as well as to gate SOin the switch translator. The various inputs of gate V0 are connected toall of the line circuits (00, 10, 20 that are served by a vertical 0 ofone of line switches 0 through 7. The inputs of gate S0 are connected tothe M leads of all line circuits (00 through 07) served by line switch0. In an analogous manner, gate V7 of the vertical translator isconnected to the M leads of all line circuits served by the seventhvertical of a line switch; gate S7 is connected to the M leads of allline circuits served by line switch 7.

All of the gates shown on FIGS. 4 are of the NAND type. The OR gates,e.g., V0, work in such a manner that any one or more input being lowwill drive the output high. The AND e.g., 409-0 or 414-1 gates operatein such a manner that all of the inputs driven high will drive theoutput low.

The output of the vertical and switch translators are designated 0through 7 and each represents a correspondingly designated switchvertical or switch number. For example, when line circuit 00 marks its Mconductor to request a connection, a ground or low potential is appliedto conductor M00 by the line circuit. This ground is extended to theupper input of gate V0 as well as to the upper input of gate SO. Withrespect to vertical translator 403, the ground on the upper inputconductor of gate V0 drives its output high which extends to the inputof gate 409-0. The high on the input of this gate drives its output lowextending to the output conductor 0 of the translator. The groundpotential (a binary 0) on this conductor indicates that a line circuitserved by a vertical 0 of a switch is currently marked. In a similarmanner, the ground or binary 0 on the input of gate SO generates a highor a binary 1 on the output of the gate which, in turn, generates a lowon the output of gate 410-0. This applies a low to output 0 of theswitch translator as an indication that the marked circuit is served bya switch 0. A low or binary 0 on the output conductor 0 of bothtranslators indicates that the line circuit now being marked is servedby vertical 0 of switch 0, in other words, line circuit 00. A low onoutput conductor 7 of each translator would indicate that the callingline circuit is connected to the seventh vertical of the seventh switch.

Further with respect to the switch translator 404, the output of each ofgates S0 through 87 is connected to gates C0 through C7 respectively,and in turn to relays CO through C7. One of the C- relays operates eachtime its associated S gate receives a marking potential at its input.Thus with respect to the connection now being described, a mark onconductor M00 generates a binary l at the output of gate SO. This causesthe output of gate C0 to go to a ground potential to operate relay C0.From an inspection of FIG. 3 it may be seen that the operation of relayC0 is required any time a connection is to be extended between lineswitch 0 and any of the trunk switches.

The output conductors of the vertical translator 403 are connected tothe inputs of the binary encoder 405 as vell as to the inputs of binarycomplement encoder 406. The binary encoder 405 responds to thetranslator outout signals and generates the binary equivalent of thenumber of the currently marked switch vertical. The vinary complementencoder 406 generates the binary comlement of the switch vertical. Withrespect to the call :onnection now being described, the ground or binaryan output 0 of the vertical translator is extended to the 31', B2 and B4gates of the complement encoder. All hree of these gates now turn offand drive their outputs nigh, i.e., to a binary I. The outputs of gatesB1, B2 and 34 remain low, a binary 0, since none of their inputs re-:eive a low from the vertical translator at this time. The nputs of theencoder gates are designated to indicate the autput of the verticaltranslator to which they are coniected. By inspection it may be seenthat the 0 output If the vertical translator is connected to the 0inputs of gates B1, B2 and B4 of the binary complementary en- :oder. Thebinary 0 signal now on the "0 output of the ranslator generates a binary1 on the output of these hree gates. Since the 0" output of thetranslator is not :onnected to any gates of binary encoder 405, theoutput )f its B1, B2 and B4 gates remain at a binary 0. Thus, it nay beseen that the output of the two encoders are com- :lementary when thenetwork receives a marking potenial from the M-lead of a single linecircuit. The binary signal on the three outputs of binary encoder 405are :xtended through the gates 411 which apply a binary 1 )1 highpotential to the inputs of relays A1, A2 and A4. these three relays,therefore remain released at this time.

The binary Os from the three outputs of the encoder 405 ire alsoextended over conductors 412 via gates 416- and l15- to the upper inputAND gates 414-1, 414-2 and l14-4. Under the conditions now beingdescribed, a bilary 0 is applied to the upper input of these three ANDgates. The binary l on the outputs of the binary com- :lementary encoderare applied over conductors 413- diectly to the lower inputs of thethree AND gates 414-. \t this time, the two inputs to each of thesethree AND gates are different and thus no AND gate turns 0N at his time.The reason for this is that each AND gate 414- :urrently receives abinary l on its lower input from en- :oder 406 and at the same time,receives a binary 0 on ts upper input from encoder 405 via gates 416-and 415-. 'n summary, with only one input lead to vertical translaor 403energized by a marking potential, the two encod- :rs 405 and 406 producecomplementary output potenials so that one input of each of AND gates414- receives t binary 1 while the other input receives a binary 0.Since he AND condition of the gates 414 occurs only when :oth inputsreceives a binary 1, no AND gate turns on it this time.

The switch translator 404, the encoders 407 and 408, gates 426-, 425-and AND gates 424- operate in a nanner analogous to that alreadydescribed, so that no ND gate 424 turns on as long as only a singlemarkng potential from any of the M-leads is received at the nput of theswitch translator 404. Specifically, for the :all connection now beingdescribed, a marking potenial is received by gate S0 on its inputconductor MOO. [his generates a binary 0 at the 0 output of the transla-;or i.e., gate 410-0. In response to this signal, the binary:omplementary encoder 408 applies binary ls via :onductors 423 to thelower inputs of AND gates 424; ind binary encoder 407 applies binary Osfrom its outits to conductors 422-, via gates 426- and 425-, to therpper input of each of AND gates 424-. Since the rpper input of each ANDgate 424- is a binary 0 and its ower input is a binary 1, no AND gateturns on.

The output of the binary encoder 407, via gates 421, :ontrols theoperated or nonoperated state of the B1, B2, and B4 relays. For thepresently described call, the output of the switch translator 404 is notconnected :0 any of the gates of encoder 407; therefore they remain n anON condition state with their output at a low or 8 binary 0. This holdsthe output of gates 421- at a binary 1 or high potential and, in turn,maintains all of the B- relays released.

With all of the A- and B-relays in a released state as a consequence ofa marking potential on conductor MOO, it may be seen from an inspectionof FIGS. 3 that the left output conductor 303 of the pulser 301 will beconnected via the break contacts of the B- and A- relays to the V0vertical control conductor of line switch 0. Also, the right outputconductor 304 of the pulser is connected via break contacts of relays E-and D- to the H0 control conductor of trunk switch 0.

Rectangle 402 contains circuitry similar to that of rectangle 401.Element 402 receives the mark signals from the M leads of the trunkcircuits and, in response thereto, maintains all of its AND gatescorresponding to AND gates 414- and 424- in an otf state so long as onlyone marking potential at a time is received.

The output conductors 427-1 and 427-2 of AND gates 414- and 424- extendto input terminals 1 and 2 of OR gate 417. The corresponding outputconductors of element 402 are designated 427-3 and 427-4 and they extendto input terminals 3 and 4 of gate 417. All of conductors 427- remain ata binary 1 or high state provided only a single marking potential isreceived by each of elements 401 and 402. The binary 1 on all ofconductors 427- holds the output of gate 417 and input of gate 418 at abinary 0. This maintains the output of gate 418 at a binary 1" which isapplied to the upper input of AND gate 420. The other input of gate 420is connected to common control which applies a binary 1 to gate 420whenever it is desired to activate the network pulser. The binary 1 onboth inputs of gate 420 generates a binary 0 at its output. This isapplied to the pulser which, in turn, generates the currents required toclose the crosspoints selected by the state of the relay contacts shownon FIG. 3.

The following describes the operation of the circuit of element 401 whentwo marking potentials are simultaneously received from the linecircuits. Let it be assumed that both line circuits 00 and 77simultaneously generate marking potentials on conductors M00 and M71.The potential on conductor M00 is applied to gate V0 of the verticaltranslator and to gate S0 of the switch translator. The markingpotential on conductor M77 is applied to gates V7 and S7. The receptionof the marking potential by gate V0 causes a binary 0 signal to appearon the 0 output of the vertical translator. This signal is applied tothe correspondingly designated inputs of gates B1, B2, and B4 of thebinary complementary encoder 406 as already described. The mark signalon conductor M77 is applied to gate V7 and causes a binary 0 to appearon output conductor 7 of the vertical translator. This signal in turn isapplied to the correspondingly designated inputs of gates B1, B2, andB4. Thus with reception of these two mark signals simultaneously, allgates of both encoders 405 and 406 are activated, and a binary 1 appearson the output of all gates. The binary ls from the outputs of theencoder 406 are applied directly to the lower inputs of each of ANDgates 414-, the binary Is from the output of encoder 405 are applied viagates 416- and 415- and appear as a binary 1 on the upper inputs of eachof AND gates 414-. Thus, under the conditions now described, all ANDgates 414- are turned on since a binary l is applied to both inputs ofeach gate. This causes a 0 to be applied to conductor 427-1 whichextends to input 1 of OR gate 417. This 0 causes the output of gate 417to generate a 1, and the output of gate 418 to generate a 0 which isapplied to alarm circuit 419 to activate it. Further, the binary 0 fromgate 418 is applied to the upper input of AND gate 420 to disable it sothat it will not respond to the binary 1 on its lower input when commoncontrol attempts to pulse the network.

The simultaneous mark signals on conductors M and M77 eflect similarcircuit actions in the circuitry activated by the switch translator 404.Thus, all of AND gates 424- turn on at this time and apply a binary 0 tothe number 2 input of gate 417.

The preceding has described the manner in which the circuit of myinvention detects double marking conditions in response to signals fromline circuit 00 and 77. In the situation just described, both verticaltranslator 403 and switch translator 404 generated double outputs. Thiscaused the binary encoder and the binary complementary encoderassociated with each translator to generate noncomplementary outputinformation which, in turn, activated the AND gates 414iand 424-.

Other combinations of double marking conditions may occur. Thus,depending upon M conductors on which the double marks appear, thecircuitry driven by the vertical translator may cause its encoders togenerate valid information while the circuitry associated with theswitch translator may cause its encoders to generate invalid ornoncomplementary information. Under such conditions, one or more ofgates 424- would be turned on while none of gates 414-, would be turnedon. The converse situation would apply whenever translator 403 is theonly one to receive double marks. In short, the pair of encoders thatgenerate the noncomplementary output information depends on thecombination of line circuits from which the simultaneous marks arereceived. Further, the specific AND gate or gates (41.4-, 424-) that areactivated in response to the noncomplementary information also dependsupon the specific combination of line circuits from which the doublemarks are received.

In a manner similar to that already described for the line circuits,rectangle 202 detects the application of simultaneous marks from morethan one trunk circuit and under such conditions applies a binary 0 toone or both of conductors 427-3 and 427-4 which extend to OR gate 417.The response of this gate and the circuitry controlled by it to thedouble marked signals from the trunks is identical to that alreadydescribed for the line circuits.

My invention also permits certain trouble conditions in the networkcontrol relays to be detected. In order to describe the manner in whichthis operation is effected let it once again be assumed that a mark isreceived from line circuit 00 on its conductor M00. In the manner prior-1y described, this signal causes a binary 1 to appear on the threeoutputs of the encoder 406 and a binary 0 to appear on the three outputsof encoder 405. The binary ls from encoder 406 are applied directly tothe lower input of all AND gates 414-. The binary 0's from the outputsof encoder 405 are applied through gates 416- and 415- and appears as abinary 0 on upper inputs of gates 414- so that none of these gates turnon. However, let it be assumed that due to trouble conditions, relay A1remains operated from a prior usage of the network path establishingcircuitry. In this case, a make contact of the relay applies a ground orbinary 0 over conductor A1 to the upper input of OR gate 415-1. This 0turns the gate OFF and causes the output of the gate to apply a binary 1to the upper input of OR gate 414.-1 to turn it ON. Gate 414-1 now turnsON even though the outputs of encoders 4.05 and 406 are complementary.The turn on of AND 414-1 generates a 0 at its output, and activates ORgate 417 and the circuitry controlled by it including alarm circuit 419in the manner already described.

Thus, my invention is advantageous in that it permits double markingconditions to be detected as well as faults in the relay controlcircuitry. In response to such trouble conditions it activates alarmcircuit 419 which specifically indicates to a craftsman the nature ofthe trouble condition. It further disables AND gate 420 so that thesystem will not respond to the marking signals and pulse the network inan attempt to establish a new network connection.

What is claimed is:

[1. In a switching system, an end marked network having a line side anda trunk side, means for establishing a path through said network inresponse to the application of a single marking potential to each ofsaid sides, means for detecting the concurrent application of aplurality of marking potentials to either of said sides, and meansresponsive to the detection of said plurality of marking potentials forpreventing the operation of said path establishing means] [2. In aswitching system, an end marked network having a line side and a trunkside, traific circuits connected to said network, means in each of saidtrafiic circuits for applying a marking potential to one of said sidesto request the establishment of a call connection through said network,means for establishing a connection path through said network betweenrequesting ones of said traflic circuits in response to the applicationof a single marking potential to each of said sides, means for detectingthe concurrent application of a plurality of marking potentials toeither of said sides, and means responsive to the detection of saidplurality of marking potentials for pre venting the operation of saidpath establishing means] 3. [The system of claim 2 in which] In aswitching syslem, an end marked network having a line side and a trunkside, trafi'ic circuits connected to said network, means in each of saidtraflic circuits for applying a marking potential to one of said sidesto request the establishment of a call connection through said network,means for establishing a connection path through said network betweenrequesting ones of said trafiic circuits in response to the applicationof a single marking pot ntial to each of said sides, means for detectingthe concurrent applicm tion of a plurality of marking potentials toeither of said sides, and means responsive to the detection of saidplurality of marking potentials for preventing the operation of saidpath establishing means, said means for detecting [comprises]comprising, a line side translator and a trunk side translator, each ofsaid translators being responsive to each marking potential received byits associated side of said network for generating an output signalidentifying the trafiic circuit applying said marking potential, andmeans in each of said translators responsive to the concurrentapplication of a plurality of marking potentials to its associated sidefor generating multiple output signals identifying the traflic circuitsapplying said plurality of potentials.

4. The system of claim 3 in which said means for establishing comprises,path determining means, and means responsive to said translator outputsignals identifying the trafiic circuits currently applying said markingpotentials for selectively operating said path determining means todetermine the network connection path to be established.

5. The system of claim 4 in which said means for preventing comprisesmeans responsive to multiple output signals from either of saidtranslators for generating an inhibit signal to prevent the operation ofsaid path establishing means.

[6. In a switching system, an end marked network having a line side anda trunk side, a plurality of appearances on each of said sides, aplurality of line circuits each of which is connected to a differentappearance on said line side, a plurality of trunk circuits each ofwhich is connected to a different appearance on said trunk side, meansin each of said circuits for applying a marking potential to its networkappearance to request a call connection path through said network, meansfor establishing a con nection path through said network between two ofsaid circuits in response to the application of a single markingpotential to each of said sides by said two circuits, means fordetecting the concurrent application of a plurality of markingpotentials to either one of said sides, and means responsive to thedetection of said plurality of marking potentials for preventing theoperation of said path establishing means] 7. [The system of claim 6 inwhich] In a switching system, an end marked network having a line sideand a trunk side, a plurality of appearances on each of said sides, aplurality of line circuits each of which is connected to a differentappearance on said line side, a plurality of trunk circuits each ofwhich is connected to a difierent appearance on said trunk side, meansin each of said circuits for applying a marking potential to its networkappearance to request a call connection path through said network, meansfor establishing a connection path through said network between two ofsaid circuits in response to the application of a single markingpotential to each of said sides by said two circuits, means for dtecting the concurrent application of a plurality of marking potentialsto either one of said sides, and means responsive to the detection ofsaid plurality of marking potentials for preventing the operation ofsaid path establishing means, said means for detecting [comprises]comprising, a line side translator and a trunk side translator, each ofsaid translators being responsive to each marking potential received byits associated side of said network for generating an output signalidentifying the circuit applying said marking potential, each of saidtranslators being further responsive to the concurrent application of aplurality of marking potentials to its associated side for generatingmultiple output signals identifying the circuits applying said pluralityof potentials.

8. The system of claim 7 in which said means for preventing comprisesmeans responsive to multiple output signals from either of saidtranslators for generating an inhibit signal to prevent the operation ofsaid path establishing means.

9. The system of claim 8 in which said means for preventing furthercomprises, a first encoder responsive to the generation of an outputsignal by each of said translators for generating an encoded signalidentifying each of said circuits currently applying a marking potentialto said network, a second encoder responsive to the generation of anoutput signal by said translators for generating an output signal thatis complementary to that of said first encoder, means including each ofsaid encoders responsive to the concurrent application of a plurality ofmarking potentials to either of said sides for causing said encoders togenerate output signals that are noncomplementary with respect to eachother, means for comparing the complementary relationship of the outputsof said encoders, means for establishing said network connection ifoutputs are complementary, and means for preventing said establishmentif said outputs are not complementary,

10. The system of claim 9 in which said means for establishingcomprises, path determining means, and means responsive to said firstencoder output signals identifying the circuits currently applying saidmarking potentials for selectively operating said path determining meansto determine the network connection path to be established.

11. The system of claim 8 in which said means for preventing furthercomprises, a line side and a trunk side encoder each of which isindividual to one of said translators, each of said encoders beingresponsive to the generation of an output signal by the translator forits side for generating an encoded signal identifying each of saidcircuits currently applying a marking potential to its side of saidnetwork, a line side and a trunk side complement encoder, each of saidcomplement encoders being responsive to the generation of an outputsignal by the translator for its side for generating an output signalthat is complementary to that of the first encoder for the same side,means including both encoders for a side responsive to the concurrentapplication of a plurality of marking potentials to said side forcausing both of said encoders to generate output signals that are notOmplementary with respect to lll each other, means for comparing theoutputs of both of the said encoder for a side, means for establishingsaid network connection if said outputs are complementary, and means forpreventing said establishment if said outputs are not complementary.

12. The system of claim 11 in which said means for establishingcomprises, path determining means, and means responsive to said lineside and trunk side encoder output signals identifying the circuitscurrently applying said marking potentials for selectively operatingsaid path determining means to determine the network connection path tobe established.

13. In a switching system, an end marked network having a line side anda trunk side, a plurality of appearances on each of said sides, aplurality of line circuits each of which is connected to a differentappearance on said line side, a plurality of trunk circuits each ofwhich is connected to a different appearance on said trunk side, meansin each of said circuits for applying a marking potential to its networkappearance to request a call connection through said network, line sideencoder means and a trunk side encoder means, each of said encoder meansbeing responsive to the application of a marking potential to itsassociated side of said network for generating a first encoded signalidentifying the circuit applying said potential to its side and forconcurrently generating a signal that is the complement of said firstsignal each of said encoder means being responsive to the concurrentapplication of a plurality of marking potentials to its associated sidefor generating a first and a second signal that are noncomplementarywith respect to each other, means including comparison means responsiveto the generation of complementary signals from both of said encodermeans for causing the establishment of a network path between the onesof said circuits currently applying said marking potentials, and meansincluding said comparison means responsive to the generation ofnoncomplementary signals by either of said encoder means for inhibitingthe establishment of network path.

14. The system of claim 13 in which said means for causing theestablishment of said path comprises path determining means, and meansresponsive to said encoder signals identifying the circuits currentlyapplying said marking potentials for selectively operating said pathdetermining means to determine the network connection path to beestablished.

15. The system of claim 14 in which path determining means comprises aplurality of path determining relays that may be selectively operated bysaid first encoded signal to determine the network path to beestablished, a contact on each of said relays for indicating theoperated state of its associated relay, and means for interconnectingeach of said contacts with said comparison means to provide a signalindicating the failure of said relay to release from a prior pathestablishing operation, said comparison means being etlective to inhibitthe establishment of a network path in response to the reception of saidfailure signal.

16. In a switching system, an end marked network having a line side anda trunk side, trafi'ic circuits connected to said sides of said network,means in each of said tralfic circuits for applying a marking potentialto one of said sides to request the establishment of a call connectionthrough said network, means responsive to each application of a singlemarking potential to a side for generating two output signals having acomplementary relationship with respect to each other, said last namedmeans being responsive to the concurrent application of a plurality ofmarking potentials to a side for generating two output signals having anoncomplementary relationship with respect to each other, means forestablishing a connection path through said network in response to thegeneration of complementary output signals, and means for preventing theoperating of said 13 path establishing means in response to thegeneration of said noncomplementary signals.

17. The system of claim 16 in which said means for establishingcomprises, path determining means, and means responsive to the first ofsaid two complementary output signals for selectively operating saidpath determining means to determine the network connection path to beestablished.

18. The method of operating a system having an end marked switchingnetwork comprising the steps of: (1) detecting the presence of eachmarking potential applied to an appearance on either side of saidnetwork, (2) generating a first encoded signal identifying each networkappearance receiving a marking potential, (3) generating a signalcomplementary to said first signal Whenever only a single potential isapplied to either of said sides, (4) generating a signal that isnoncomplementary to said first signal whenever a plurality of markingpotentials are concurrently applied to either of said sides, (5)establishing a network path between the currently marked ones of saidappearances in response to the generation of said complementary signal,and (6) preventing the establishment of said path in response to thegeneration of said noncomplernentary signal.

19. The method of claim 18 in combination with the further step of:applying said first encoded signal to path determining circuitry todetermine the network path that is to be established between thecurrently marked appearances.

20. In a switching system having an end marked network, first encodingmeans, second encoding means, said second encoding means beingcomplementary to said first encoding means, means responsive to anetwork marking potential for applying a signal to said first and saidsecond encoding means, means for comparing the outputs of said first andsecond encoding means, and means for establishing a path through thenetwork only on detection by said comparing means of complementaryoutputs from said first and second encoding means.

21. In a switching system, circuitry in accordance with claim 20 whereinsaid first and second encoding means provide noncomplernentary outputswhen more than one signal is applied concurrently to said first andsecond encoding means further comprising, means for preventing theestablishing of a path through the network on detection by saidcomparing means of noncomplementary outputs from said first and secondencoding means.

References Cited 11/1967 Voegtlen et al. 179l7$.2l 6/1971 White 179-19GF WILLIAM C. COOPER, Primary Examiner US. Cl. X.R. l79l8 GF

